PORA

Core Logic 325$ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description PORA is a power-on-reset. When power is applied, the POR output is asserted low for at least 2 microseconds after the logic circuits become operational. The active high RESET input also drives the POR signal to its active low state. Since the PORA is a corner function cell the RESET pin must be driven through the core. For proper operation, user-designed external circuitry must provide a VDD power slew rate of at least one volt per microsecond. This ensures that the reset pulse will be properly output when VDD falls to zero and immediately returns to its valid range. Logic Symbol PORA Truth Table Pin Loading RESET R POR C RESET L H POR H L RESET Load 4.4 eql HDL Syntax Verilog .................... PORA inst_name (RESET, POR); VHDL...................... inst_name: PORA port map (RESET, POR); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 1917.7 Un...