PL585-88

(Preliminary) PL585-88 19MHz to 800MHz Low Phase-Noise VCXO FE AT UR E S  < 0.5ps RMS phase jitter (12kHz to 20MHz) at 622.08MHz  25ps max peak to peak period jitter  Ultra Low-Power Consumption  < 90mA @622MHz PECL output  <10A at Power Down (PDB) Mode  Input Frequency:  Fundamental Crystal: 19MHz to 40MHz  Output Frequency:  19MHz to 800MHz output.  Output type: LVPECL  High Linearity VCXO: <10% linearity  Pullability: ±150 ppm  Programmable OE input polarity selection.  Power Supply: 3.3V, ±10%  Operating Temperature Ranges:  Commercial: 0C to 70C  Industrial: -40C to 85C  Available in Die or Wafer DESCRIPTION The PL585 is a Dual LC core monolithic IC clock, capable of maintaining sub-picoseconds RMS phase jitter, while covering a wide frequency output range up to 800MHz, without the use of external components. The high performance and high frequency output is achieved using a low cost fundamental crystal of between 19MHz and 40 MHz. The PL585 is designed to address the demanding requirements of high performance applications such as Fiber Channel, serial ATA, Ethernet, SAN, SONET/SDH, etc. PIN CONFIGURATION 65 mil 88.6 mil XIN, FIN XOUT VCON/ 9 SCLK 8 Die ID OE/PDB/ SDIO DNC 10 11 GND_ANA GND_DIG GND_BUF 12 13 14 (1650,2250) 7 6 VDD_ANA 5 VDD_DIG 4 VDD_BUF 3 QB 2 VDD_BUF 1Q (0,0) PL585 DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 65 x 88.6 mil GND 80 micron x 80 micron 8 mils OUTPUT ENABLE CONTROL OE Select...