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P51XAG30KBBD Datasheet

Part Number P51XAG30KBBD
Manufacturers NXP
Logo NXP
Description XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless / watchdog / 2 UARTs
Datasheet P51XAG30KBBD DatasheetP51XAG30KBBD Datasheet (PDF)

INTEGRATED CIRCUITS XA-G3 XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs Product specification Supersedes data of 1998 Aug 14 IC25 Data Handbook 1999 Apr 07 Philips Semiconductors Philips Semiconductors Product specification XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs XA-G3 FAMILY DESCRIPTION The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle th.

  P51XAG30KBBD   P51XAG30KBBD






XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless / watchdog / 2 UARTs

INTEGRATED CIRCUITS XA-G3 XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs Product specification Supersedes data of 1998 Aug 14 IC25 Data Handbook 1999 Apr 07 Philips Semiconductors Philips Semiconductors Product specification XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs XA-G3 FAMILY DESCRIPTION The Philips Semiconductors XA (eXtended Architecture) family of 16-bit single-chip microcontrollers is powerful enough to easily handle the requirements of high performance embedded applications, yet inexpensive enough to compete in the market for high-volume, low-cost applications. The XA family provides an upward compatibility path for 80C51 users who need higher performance and 64k or more of program memory. Existing 80C51 code can also easily be translated to run on XA microcontrollers. The performance of the XA architecture supports the comprehensive bit-oriented operations of the 80C51 while incorporating support for multi-tasking operating systems and high-level languages such as C. The speed of the XA architecture, at 10 to 100 times that of the 80C51, gives designers an easy path to truly high performance embedded control. The XA architecture supports: • Instruction set tailored for high level language support • Multi-tasking and real-time executives that include up to 32 vectored interrupts, 16 software traps, segmented data memory, and banked registers to support context switching • Low power operation, whic.


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