OR3LP26B

Data Sheet March 2000 ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation, coupled with the high bandwidth of an industry-standard PCI interface. The ORCA OR3LP26B (a member of the Series 3+ FPSC family) provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions. s Four internal FIFOs individually buffer both directions of both the Master and Target interfaces: — Both Master FIFOs are 64 bits wide by 32 bits deep. — Both Target FIFOs are 64 bits wide by 16 bits deep. Capable of no-wait-state, full-burst PCI transfers in either direction, on either the Master or Target interface. The dual 64-bit data paths extend into the FPGA logic, permitting full-bandwidth, simultaneous bidirectional data transfers of up to 528 Mbytes/s to be sustained indefinitely. Can be configured to provide either two 64-bit buses (one in each direction) to be multiplexed between Master and Target, or four independent 32-bit buses. Provides many hardware options in the PCI core that are set during FPGA logic configuration. Operates within the requirements of the PCI 5 V and 3.3 V signaling environments and 3.3 V commercial environmental conditions, allowing the same device to be used in 5 V or 3.3 V PCI systems....