ON52

21[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Description ON5x is a family of OR-NAND circuits consisting of one 3-input OR gate and one 2-input OR gate into a 2-input NAND gate. Logic Symbol Truth Table A ON5x ABCDEQ B L L LXXH C Q XXXL LH D All other combinations L E Core Logic HDL Syntax Verilog .................... ON5x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: ON5x port map (Q, A, B, C, D, E); Pin Loading Pin Name A B C D E ON52 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ON54 1.0 1.0 1.0 1.0 1.0 ON56 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ON52 4.0 TBD 8.3 ON54 5.0 TBD 8.8 ON56 10.0 TBD 19.5 a. See page 2-15 for power equation. 3-189 21[ ® $0,+*  PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 ON52 From: Any Input To: Q tPLH tPHL ...