JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes
Power...
NT5CB128M8FN PDF File
