NDC651N

March 1996 NDC651N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features 3.2A, 30V. RDS(ON) = 0.09Ω @ VGS = 4.5V RDS(ON) = 0.06Ω @ VGS = 10V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________ 4 3 5 2 6 1 Absolute Maximum Ratings T A = 25°C unless otherwise note Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c) (Note 1a) NDC651N 30 20 3.2 15 1.6 1 0.8 -55 to 150 Units V V A W TJ,TSTG Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (...