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NBSG53A Datasheet

Part Number NBSG53A
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider
Datasheet NBSG53A DatasheetNBSG53A Datasheet (PDF)

NBSG53A 2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS* The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaCommt family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package. The NBSG53A.

  NBSG53A   NBSG53A






2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

NBSG53A 2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS* The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaCommt family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package. The NBSG53A is a device with data, clock, OLS*, reset, and select inputs. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device. Features • Maximum Input Clock Frequency (DFF) > 8 GHz Typical (See Figures 3, 5, 7, 9, and 10) • Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical (See Figures 4, 6, 8, 9, and 10) • 210 ps Typical Propagation Delay (OLS = FLOAT) • 45 ps Typical Rise and Fall Times (OLS = FLOAT) • DIV/2 Mode (Active with Select Low) • DFF Mode (Active with Select High) • Selectable Swing .


2007-04-24 : TVG9470    M402101BP    2SK1653    OTI-033    OTI-031    OTI-032    OTI-034    P181TG5-2V-T    SI2401    LH5493   


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