NB3N3020
3.3 V, LVPECL/LVCMOS Clock Multiplier
Description The NB3N3020 is a high precision, low phase noise selectabl...
NB3N3020
3.3 V, LVPECL/LV
CMOS Clock Multiplier
Description The NB3N3020 is a high precision, low phase noise selectable clock
multiplier. The device takes a 5 – 27 MHz fundamental mode parallel resonant crystal or a 2 − 210 MHz LV
CMOS single ended clock source and generates a differential LVPECL output and a single ended LV
CMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri−level (Low, Mid, High) LV
CMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. The LV
CMOS/LVTTL output enable (OE1) tri−states the LV
CMOS/LVTTL clock output (CLK1) when low. When the LVTTL/LV
CMOS output enable (OE2) is LOW, LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin package.
Features
Selectable Clock Multiplier
External Loop Filter is Not Required
LVPECL Differential Output
LV
CMOS/ LVTTL Outputs
RMS Period Jitter of 5 ps
Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:
Offset
Noise Power
100 Hz
−95 dBc/Hz
1 kHz
−107 dBc/Hz
10 kHz
−112 dBc/Hz
100 kHz
−117 dBc/Hz
1 MHz
−117 dBc/Hz
10 MHz
−134 dBc/Hz
Operating Range 3.3 V ±10%
Industrial Temperature Range −40°C to +85°C
These are Pb−Free Devices
http://onsemi.com
16
1 TSSOP−16 DT SUFFIX CASE 948F
MARKING DIAGRAM
16
NB3N 3020 ALYWG
1G
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
(*Note: Microdot may be in eithe...