MVA60000

MVA60000 MVA60000 Series 1.4 Micron CMOS MEGACELL ASICs DS5499 ISSUE 3.1 March 1991 GENERAL DESCRIPTION Very large scale integrated circuits, requiring large RAM and ROM blocks, often do not suit even high complexity gate arrays, such as Zarlink Semiconductors' CLA60000 series. MVA60000 Megacell ASICs provide RAM, ROM, and PLA macros, optimised for minimum area, which are compiled to match system requirements exactly. Based on an advanced CMOS process using stacked contacts and vias to produce cells virtually 'transparent' to interconnection routing, MVA60000 allows systems up to 80,000 gates to be integrated on a single silicon chip. With ever-decreasing lifecycles many systems need a clear migration route to higher technology. MVA60000 designs are fully netlist compatible with 1.4 micron CLA60000 array designs, which provides a clear path for upgrading systems by integration of large RAM and ROM blocks, and analog elements. Compatibility extends to Zarlink Semiconductors' new sub-micron CMOS ASIC products, such as the CLA70000 gate array family. Operation over the full military temperature range is easily achieved, even for complex designs, since Zarlink Semiconductors' process allows a maximum junction temperature of 150 degrees C. FEATURES s Up to 80,000 used gates at <9µ W/MHz per loaded gate (Fanout=2) allows integration of entire systems. s 1.1 micron channel length (1.4 micron drawn) dual layer metal, silicon gate CMOS process, with double polysili con option fo...