MTD3055VL

MOTOROLA Designer's SEMICONDUCTOR TECHNICAL DATA Order this document by MTD3055VL/D TMOS V Power Field Effect Transistor DPAK for Surface Mount TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. New Features of TMOS V On–resistance Area Product about One–half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than E–FET Predecessors Features Common to TMOS V and TMOS E–FETS Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS E–FET Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltag — Single Pulse (tp ≤ 50 ms) Drain Current — Continuous @ 2...