MT47H128M4

512Mb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H128M4 – 32 Meg x 4 x 4 banks MT47H64M8 – 16 Meg x 8 x 4 banks MT47H32M16 – 8 Meg x 16 x 4 banks Features VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V JEDEC-standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option 4n-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 DLL to align DQ and DQS transitions with CK 4 internal banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 tCK Selectable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8192-cycle refresh On-die termination (ODT) Industrial temperature (IT) option RoHS-compliant Supports JEDEC clock jitter specification Options1 Configuration – 128 Meg x 4 (32 Meg x 4 x 4 banks) – 64 Meg x 8 (16 Meg x 8 x 4 banks) – 32 Meg x 16 (8 Meg x 16 x 4 banks) FBGA package (Pb...