MT46V32M4

m 128Mb: x4, x8, x16 DDR SDRAM o Features c . U 4 t Double Data Rate (DDR) SDRAM e e8 Meg x 4 x 4 Banks MT46V32M4h – S – 4 Meg x 8 x 4 Banks MT46V16M8 a MT46V8M16 at – 2 Meg x 16 x 4 Banks .D w w Features Options Marking w For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/sdram VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR 400) Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data (x16 has two – one per byte) Programmable burst lengths: 2, 4, or 8 Auto Refresh and Self Refresh Modes Longer lead TSOP for improved reliability (OCPL) 2.5V I/O (SSTL_2 compatible) Concurrent auto precharge option is supported tRAS lockout supported (tRAP = tRCD) Table 1: Configuration Addressing Configuration Refresh Count Row Addressing Bank Addressing Column Addressing Table 2: Key Timing Parameters m o .c U 4 t e e h S a t a .D w w w Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 ban...