MSM56V16800D

E2G1047-18-25 ¡ Semiconductor MSM56V16800D/DH ¡ Semiconductor ThisMSM56V16800D/DH version: Mar. 1998 Pr el im in ar y 2-Bank ¥ 1,048,576-Word ¥ 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16800D/DH is a 2-bank ¥ 1,048,576-word ¥ 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-bank ¥ 1,048,576-word ¥ 8-bit configuration 3.3 V power supply, ± 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode – CAS latency (1, 2, 3) – CAS latency (2, 3)*1 – Burst length (1, 2, 4, 8, full page) – Burst length (1, 2, 4, 8)*1 – Data scramble (sequential, interleave) *1 : H version only. CBR auto-refresh, Self-refresh capability Package: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800D/DH-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM56V16800D-10 MSM56V16800D-12 MSM56V16800DH-15 Max. Frequency 100 MHz 83 MHz 66 MHz Access Time (Max.) tAC2 9 ns 14 ns 9 ns tAC3 9 ns 10 ns 9 ns 1/30 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) MSM56V16800D/DH VCC DQ1 VSSQ DQ2 VCCQ DQ3 VSSQ DQ4 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22  DQM DQi VCC VSS VCCQ VSSQ NC 44 VSS 43 DQ8 42 VSSQ 41 DQ7 40 VCCQ 3...