MSM56V16160DH

E2G1049-18-33 ¡ Semiconductor MSM56V16160D/DH ¡ Semiconductor ThisMSM56V16160D/DH version: Mar. 1998 Pr el im in ar y 2-Bank ¥ 524,288-Word ¥ 16-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16160D/DH is a 2-bank ¥ 524,288-word ¥ 16-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-bank ¥ 524,288-word ¥ 16-bit configuration 3.3 V power supply, ± 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode – CAS latency (1, 2, 3) – CAS latency (2, 3)*1 – Burst length (1, 2, 4, 8, full page) – Burst length (1, 2, 4, 8)*1 – Data scramble (sequential, interleave) *1 : H version only. CBR auto-refresh, Self-refresh capability Package: 50-pin 400 mil plastic TSOP (Type II) (TSOPII50-P-400-0.80-K) (Product : MSM56V16160D/DH-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM56V16160D-10 MSM56V16160D-12 MSM56V16160DH-15 Max. Frequency 100 MHz 83 MHz 66 MHz Access Time (Max.) tAC2 9 ns 14 ns 9 ns tAC3 9 ns 10 ns 9 ns 1/30 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 DQ8 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 MSM56V16160D/DH   10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 VSS 49 DQ16 48 DQ15 47 VSSQ 46 DQ14 45 DQ13...