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MPC2005 Datasheet

Part Number MPC2005
Manufacturers Motorola
Logo Motorola
Description (MPC2004 / MPC2005) 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
Datasheet MPC2005 DatasheetMPC2005 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2004/D Advance Information 256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72.

  MPC2005   MPC2005






Part Number MPC2004
Manufacturers Motorola
Logo Motorola
Description (MPC2004 / MPC2005) 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
Datasheet MPC2005 DatasheetMPC2004 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2004/D Advance Information 256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72.

  MPC2005   MPC2005







Part Number MPC2003
Manufacturers Motorola
Logo Motorola
Description (MPC2002 / MPC2003) 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems
Datasheet MPC2005 DatasheetMPC2003 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2002/D 256KB and 512KB BurstRAM™ Secondary Cache Module for PowerPC™ – Based Systems The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initi.

  MPC2005   MPC2005







Part Number MPC2002
Manufacturers Motorola
Logo Motorola
Description (MPC2002 / MPC2003) 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems
Datasheet MPC2005 DatasheetMPC2002 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2002/D 256KB and 512KB BurstRAM™ Secondary Cache Module for PowerPC™ – Based Systems The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initi.

  MPC2005   MPC2005







Part Number MPC2001
Manufacturers Motorola
Logo Motorola
Description 256KB Asynchronous Secondary Cache Module for PowerPC
Datasheet MPC2005 DatasheetMPC2001 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2001/D 256KB Asynchronous Secondary Cache Module for PowerPC™ The MPC2001 is designed to provide asynchronous 256KB L2 cache for the PowerPC 60x processors. The module is configured as 32K x 64 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses eight of Motorola’s MCM6206 CMOS RAMs. Eight write enables are provided for byte write control. The cache is designed to interface with the PowerPC 60x bus .

  MPC2005   MPC2005







(MPC2004 / MPC2005) 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2004/D Advance Information 256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits. Bursts can be initiated with the SRAMADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the SRAMCNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in–depth description of the cache module. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. These cache modules are plug and pin compatible with the MPC2006, a 1MB synchronous module also designed for the PReP and CHRP specifications. They are also co.


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