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ML6698 Datasheet

Part Number ML6698
Manufacturers Micro Linear
Logo Micro Linear
Description 100BASE-TX Physical Layer with 5-Bit Interface
Datasheet ML6698 DatasheetML6698 Datasheet (PDF)

May 1997 ML6698* 100BASE-TX Physical Layer with 5-Bit Interface GENERAL DESCRIPTION The ML6698 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6698 is well suited for adapter card applications using the DEC 21143, the Macronix MX98713, or equivalent Media Access Controllers (MACs). The ML6698 may be used in other 100BASE-TX applications requiring the 5-bit interface as well as FDDI-over-copper applications. The.

  ML6698   ML6698






Part Number ML6697
Manufacturers Micro Linear
Logo Micro Linear
Description 100BASE-TX Physical Layer with MII
Datasheet ML6698 DatasheetML6697 Datasheet (PDF)

July 1997 PRELIMINARY ML6697 100BASE-TX Physical Layer with MII GENERAL DESCRIPTION The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). The ML6697 functionality includes 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive.

  ML6698   ML6698







Part Number ML6696
Manufacturers Micro Linear
Logo Micro Linear
Description 100BASE-X Fiber Physical Layer
Datasheet ML6698 DatasheetML6696 Datasheet (PDF)

December 1998 ML6696* 100BASE-X Fiber Physical Layer GENERAL DESCRIPTION The ML6696 implements the complete physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the MII (Media Independent Interface) for interface to upper-layer silicon. The ML6696 integrates the data quantizer and the LED driver, allowing the use of low cost optical PMD components. The ML6696 includes 4B/5B encoder/decoder, 125MHz clock recovery/clock generation, LED driver, and a data qua.

  ML6698   ML6698







Part Number ML6695
Manufacturers Micro Linear
Logo Micro Linear
Description 100BASE-X Fiber Physical Layer With 5-bit Interface
Datasheet ML6698 DatasheetML6695 Datasheet (PDF)

December 1998 PRELIMINARY ML6695 100BASE-X Fiber Physical Layer With 5-bit Interface GENERAL DESCRIPTION The ML6695 implements the physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the 5-bit (or symbol) interface for interface to upper-layer silicon. The ML6695 integrates the data quantizer and the LED driver, allowing the use of low cost optical PMD components. The ML6695 includes 125MHz clock recovery/clock generation, an LED driver, and a data quanti.

  ML6698   ML6698







Part Number ML6694
Manufacturers Micro Linear
Logo Micro Linear
Description 100BASE-TX Physical Layer with 5-Bit Interface
Datasheet ML6698 DatasheetML6694 Datasheet (PDF)

May 1997 ML6694* 100BASE-TX Physical Layer with 5-Bit Interface GENERAL DESCRIPTION The ML6694 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6694 is well suited for repeater applications using repeater controllers with the 5-bit interface. The ML6694 may also be used in FDDIover-copper applications. The ML6694 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correct.

  ML6698   ML6698







100BASE-TX Physical Layer with 5-Bit Interface

May 1997 ML6698* 100BASE-TX Physical Layer with 5-Bit Interface GENERAL DESCRIPTION The ML6698 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6698 is well suited for adapter card applications using the DEC 21143, the Macronix MX98713, or equivalent Media Access Controllers (MACs). The ML6698 may be used in other 100BASE-TX applications requiring the 5-bit interface as well as FDDI-over-copper applications. The ML6698 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correction and MLT-3/10BASE-T transmitter. FEATURES s s s s s s s s 5-bit (or symbol) parallel interface Compliant to IEEE 802.3u 100BASE-TX standard Compliant to ANSI X3T12 TP-PMD (FDDI) standard Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY 125MHz receive clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation *Some Packages Are End Of Life As Of August 1, 2000 BLOCK DIAGRAM (PLCC Pin Configuration) 41 40 10BTTXINP 44 TXC CLOCK SYTHESIZER 10BTTXINN TPOUTP 2 3 4 5 6 TSM4 TSM3 TSM2 TSM1 TSM0 CLOCK AND DATA RECOVERY TPINP EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX DESERIALIZER RSM2 RSM1 RSM0 CONTROL LOGIC CMREF RGMSET SDO TPINN SERIALIZER NRZ TO NRZI AND NRZI TO MLT-3 ENCODER 100BASE-TX/10BASE-T TWISTED PAIR DRIVER TPOUTN RTSET 34 33 31 38 37 39 30 24 16 8 .


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