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MK50H28 Datasheet

Part Number MK50H28
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description MULTI LOGICAL LINK FRAME RELAY CONTROLLER
Datasheet MK50H28 DatasheetMK50H28 Datasheet (PDF)

® MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). Local Management Link Protocol with optional Bi-directional message processing. Detects and indicates service-affecting errors in the timing or content of events. Programmable Timers/Counters: nT1/T39.

  MK50H28   MK50H28






Part Number MK50H27
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description Signalling System 7 Link Controller
Datasheet MK50H28 DatasheetMK50H27 Datasheet (PDF)

MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with MK50H25 (X.25/LAPD), MK50H29 (SDLC), and MK50H28(Frame Relay). System clock rates up to 33 MHz (MK50H27 33), or 25 MHz (MK50H27 - 25). Data rate up to 4 Mbps conti.

  MK50H28   MK50H28







Part Number MK50H25
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description HIGH SPEED LINK LEVEL CONTROLLER
Datasheet MK50H28 DatasheetMK50H25 Datasheet (PDF)

MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Complete Level 2 implementation compatible with X.25 LAPB, ISDN LAPD, X.32, and X.75 Protocols. Han.

  MK50H28   MK50H28







MULTI LOGICAL LINK FRAME RELAY CONTROLLER

® MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). Local Management Link Protocol with optional Bi-directional message processing. Detects and indicates service-affecting errors in the timing or content of events. Programmable Timers/Counters: nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 and dN1 for the LMI/LIV channel. Provides Error Counters for the LMI channel and Congestion Statistics for all the active channels. LMI/LIV Frames can be transmitted/received on DLCI 0 or 1023. Supports reception of up to 4 octets of address field with a maximum of 8192 active channels or DLCIs (Data Link Connection Identifiers) Priority DLCI scheme for channels requiring higher rate of service. Buffer Management includes: - Initialization Block - Address Look Up Table - Context Table - Separate Receive and Transmit Rings of variable size for each active channel On chip DMA control with programmable burst length. Handles all HDLC frame formatting: - Zero bit insertion and deletion - FCS (CRC) generation and detection - Frame delimiting with flags Programmable minimum frame spacing on transmission (1-62 flags between frames). Selectable FCS (CRC) of 16 or 32 bits. Testing Facilities: Internal Loopback, Silent Loopback, Clockless Loopback, and Se.


2005-05-07 : MJ11021    MJ11021    MJ11021    MJ11022    MJ11022    MJ11028    MJ11028    MJ11028    MJ11029    MJ11029   


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