MGP3006X

GHz PLL with I2C Bus and Four Chip Addresses MGP 3006X Bipolar IC Features q q q q q q 1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 2 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology P-DSO-14-1 Type MGP 3006X MGP 3006X Ordering Code Q67000-H5114 Q67006-H5114 Package P-DSO-14-1 (SMD) P-DSO-14-1 Tape & Reel (SMD) Combined with a VCO (tuner), the MGP 3006X device, with four hard-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with PLL-frequency synthesis tuning. The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillator between 16 and 1300 MHz in increments of 62.5 kHz, and, with a 2.4-GHz prescaler 1/2, in the TV-SAT band in increments of 125 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The I2C Bus noise immunity has been improved by a factor of 10 compared to the SDA 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing the higher-order harmonics, which reduces the moiré noise considerably. Semiconductor Group 1 04.93 MGP 3006X Circuit Description Tuning Section UHF/VHF REF The tuner signal is capacitively coupled at the UHF/VHF-input and subsequently amplified. The reference input REF should be decoupled to ground using a capacitor of low series inductance. The signal ...