MC74F539

MC54/74F539 DUAL 1-OF-4 DECODER WITH 3-STATE OUTPUTS The MC54 / 74F539 contains two independent decoders. Each accepts two Address (A0 – A1) input signals and decodes them to select one of four mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active HIGH (P = L) or active LOW (P = H). An active LOW input Enable (E) is available for data demultiplexing; data is routed to the selected output in non-inverted form in the active LOW mode or in inverted form in the active HIGH mode. A HIGH Signal on the active LOW Output Enable (OE) input forces the 3-state outputs to the high impedance state. DUAL 1-OF-4 DECODER WITH 3-STATE OUTPUTS FAST™ SCHOTTKY TTL Demultiplexing Capability 3-State Outputs Two Completely Independent 1-of-4 Decoders Input Clamp Diodes Limit High Speed Termination Effects ESD Protection > 4000 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC O3b A1b A0b 20 19 18 17 Eb 16 Ea 15 OEa Pa 14 13 O0a O1a 12 11 20 1 J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 1 2 3 4 Pb 5 6 7 8 9 10 20 1 O2b O1b O0b OEb A0a A1a O3a O2a GND DW SUFFIX SOIC CASE 751D-03 LOGIC DIAGRAM (1/2 SHOWN) A1 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC A0 E LOGIC SYMBOL 13 6 7 P A0 A1 P 15 14 E DECODER a OE O0 O1 O2 O3 12 11 9 8 4 17 18 OE 16 O0 O1 O2 O3 5 E DECODER b OE Please note that this diagram is provided only for the understanding of logic operations and should not be used ...