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MC74ACT377 Datasheet

Part Number MC74ACT377
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Octal D Flip-Flop
Datasheet MC74ACT377 DatasheetMC74ACT377 Datasheet (PDF)

Octal D Flip-Flop with Clock Enable MC74AC377, MC74ACT377 The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time.

  MC74ACT377   MC74ACT377






Part Number MC74ACT377
Manufacturers Motorola
Logo Motorola
Description OCTAL D FLIP-FLOP
Datasheet MC74ACT377 DatasheetMC74ACT377 Datasheet (PDF)

MC74AC377 MC74ACT377 Octal D FlipĆFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop’s Q output. The CE input must be stable only one setup time p.

  MC74ACT377   MC74ACT377







Octal D Flip-Flop

Octal D Flip-Flop with Clock Enable MC74AC377, MC74ACT377 The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features • Ideal for Addressable Register Applications • Clock Enable for Address and Data Synchronization Applications • Eight Edge-Triggered D Flip-Flops • Buffered Common Clock • Outputs Source/Sink 24 mA • See MC74AC273 for Master Reset Version • See MC74AC373 for Transparent Latch Version • See MC74AC374 for 3-State Version • ACT377 Has TTL Compatible Inputs • MSL = 1 for all Surface Mount • Chip Complexity: 292 FETs or 73 Gates • These are Pb−Free Devices DATA SHEET www.onsemi.com 1 SOIC−20W DW SUFFIX CASE 751D MARKING DIAGRAMS 20 XXXXXX AWLYYWWG 1 1 TSSOP−20 DT SUFFIX CASE 948E 20 XXXX XXXX ALYWG G 1 XXXXXX = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. V.


2016-12-27 : MC74HCT4852A    M74HCT4052    MAX31856    AM2280    AM1280    STP40N10FI    G6265    STP40N10    PIC16LF1579    SH367103   


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