DatasheetsPDF.com

MC74AC74 Datasheet

Part Number MC74AC74
Manufacturers Motorola
Logo Motorola
Description DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
Datasheet MC74AC74 DatasheetMC74AC74 Datasheet (PDF)

www.DataSheet4U.com MC74AC74 MC74ACT74 Dual DĆType Positive EdgeĆTriggered FlipĆFlop The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been p.

  MC74AC74   MC74AC74






Part Number MC74AC74
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Dual D-Type Positive Edge-Triggered Flip-Flop
Datasheet MC74AC74 DatasheetMC74AC74 Datasheet (PDF)

Dual D-Type Positive Edge-Triggered Flip-Flop MC74AC74, MC74ACT74 The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data inpu.

  MC74AC74   MC74AC74







DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

www.DataSheet4U.com MC74AC74 MC74ACT74 Dual DĆType Positive EdgeĆTriggered FlipĆFlop The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH • Outputs Source/Sink 24 mA • ′ACT74 Has TTL Compatible Inputs VCC 14 CD2 13 D2 12 CP2 11 SD2 10 Q2 9 Q2 8 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP N SUFFIX CASE 646-06 PLASTIC CD1 D1 Q1 CP1 S Q D1 1 SD 2 CP2 Q2 D2 C Q D2 2 PIN NAMES D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs D SUFFIX CASE 751A-03 PLASTIC 1 CD1 2 D1 3 CP1 4 SD1 5 Q1 6 Q1 7 GND LOGIC SYMBOL TRUTH TABLE (Each Half) Inputs SD L H L H H H CD H L L H H H CP X X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0 Q1 SD1 D1 Q1 CD1 CP1 L H = HIGH Voltage Level L = LOW Voltage.


2006-10-14 : CS901x    AN1001    AN908    CNZ1105    F1710-305V    F1710-250V    GP1A35R    H7N0308AB    HA16148PS    HA16686MP   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)