MC68341

Parts Not Suitable for New Designs For Additional Information End-Of-Life Product Change Notice Order this document by MC68341UMAD/AD Microprocessor and Memory Technologies Group MC68341 ADDENDUM TO MC68341 Integrated Processor User's Manual April 19, 1995 This addendum to the initial release of the MC68341UM/AD User’s Manual provides corrections to the original text, plus additional information not included in the original. This document and other information on this product is maintained on the AESOP BBS, which can be reached at (800)843-3451 (from the US and Canada) or (512)891-3650. Configure modem for up to 14.4Kbaud, 8 bits, 1 stop bit, and no parity. Terminal software should support VT100 emulation. Internet access is provided by telneting to pirs.aus.sps.mot.com [129.38.233.1] or through the World Wide Web at http://pirs.aus.sps.mot.com. 1. Signal Index On page 2-4, Table 2-4, the QSPI serial clock QSCLK should be listed as an I/O signal. At the bottom of Table 2-5, FC3/DTC is an output-only signal. 2. Operand Alignment On page 3-9, last paragraph, change the first two lines to: “The CPU32 restricts all operands (both data and instructions) to be word-aligned. That is, word and long-word operands must be located on a word boundary.” Long-word operands do not have to be long-word aligned. 3. WE on Fast Termination On page 3-17, Figure 3-6, UWE and LWE do not assert for fast termination writes. 4. Write Cycle Timing Waveforms On page 3-25, the M68300 write cycl...