MC10H161

www.DataSheet4U.com MC10H161 Binary to 1−8 Decoder (Low) Description The MC10H161 provides parallel decoding of a three bit binary word to one of eight lines. The MC10H161 is useful in high−speed multiplexer/demultiplexer applications. The MC10H161 is designed to decode a three bit input word to one of eight output lines. The MC10H161 output will be low when selected while all other output are high. The enable inputs, when either or both are high, force all outputs high. The MC10H161 is a true parallel decoder. This eliminates unequal parallel path delay times found in other decoder designs. These devices are ideally suited for multiplexer/demultiplexer applications. Features http://onsemi.com MARKING DIAGRAMS* 16 MC10H161L AWLYYWW CDIP−16 L SUFFIX CASE 620A 1 Propagation Delay, 1.0 ns Typical Power Dissipation, 315 mW Typical (same as MECL 10K™) Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) Voltage Compensated MECL 10K Compatible Pb−Free Packages are Available* DIP PIN ASSIGNMENT VCC1 E0 Q3 Q2 Q1 Q0 A VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 E1 Pin assignment is for Dual−in−Line C Package. For PLCC pin assignment, see Q4 the Pin Conversion Tables on page 18 of Q5 16 16 1 PDIP−16 P SUFFIX CASE 648 1 MC10H161P AWLYYWWG 10H161 ALYWG Q6 Q7 B the ON Semiconductor MECL Data Book (DL122/D). SOEIAJ−16 CASE 966 1 20 LOGIC DIAGRAM E0 2 E1 15 VCC1 = Pin 1 VCC2 = Pin 16 VEE = Pin 8 A 7 6 Q0 ENABLE INPUTS 5 Q1 E1 E0 L L L L 4 Q2 ...