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MC10ELT24 Datasheet

Part Number MC10ELT24
Manufacturers Motorola
Logo Motorola
Description TTL to Differential ECL Translator
Datasheet MC10ELT24 DatasheetMC10ELT24 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential ECL Translator The MC10ELT/100ELT24 is a TTL to differential ECL translator. Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT24 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT24 is available in b.

  MC10ELT24   MC10ELT24






Part Number MC10ELT24
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description TTL to Differential ECL Translator
Datasheet MC10ELT24 DatasheetMC10ELT24 Datasheet (PDF)

MC10ELT24, MC100ELT24 5V TTL to Differential ECL Translator Description The MC10ELT/100ELT24 is a TTL to differential ECL translator. Because ECL levels are used a +5 V, −5.2 V (or −4.5 V) and ground are required. The small outline 8−lead package and the single gate of the ELT24 makes it ideal for those applications where space, performance and low power are at a premium. The 100 Series contains temperature compensation. Features • 0.8 ns tPHL, 0.95 ns tPLH Typical Propagation Delay • PNP TTL I.

  MC10ELT24   MC10ELT24







TTL to Differential ECL Translator

MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential ECL Translator The MC10ELT/100ELT24 is a TTL to differential ECL translator. Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT24 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT24 is available in both ECL standards: the 10ELT is compatible with MECL 10H logic levels while the 100ELT is compatible with ECL 100K logic levels. • 1.2ns Typical Propagation Delay • Differential PECL Outputs • Small Outline SOIC Package • PNP TTL Inputs for Minimal Loading • Flow Through Pinouts LOGIC DIAGRAM AND PINOUT ASSIGNMENT VEE 1 TTL D2 NC 3 8 VCC 7Q ECL 6Q NC 4 5 GND MC10ELT24 MC100ELT24 8 1 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 PIN DESCRIPTION PIN Q D VCC VEE GND FUNCTION Diff ECL.


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