MC10171

MC10171 Dual Binary to 1-4 Decoder (Low) The MC10171 is a binary coded 2 line to dual 4 line decoder with selected outputs low. With either E0 or E1 high, the corresponding selected 4 outputs are high. The common enable E, when high, forces all outputs high. PD = 325 mW typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM E0 14 10 Q0 3 11 Q0 2 12 Q0 1 A9 13 Q0 0 3 Q1 3 B7 4 Q1 2 www.DataSheet4U.com http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 MC10171P AWLYYWW 1 10171 AWLYYWW MC10171L AWLYYWW PLCC–20 FN SUFFIX CASE 775 E 15 E1 2 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 5 Q1 1 6 Q1 0 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week DIP PIN ASSIGNMENT VCC1 E1 OUTPUTS Q13 Q01 H L H H H H H Q02 H H L H H H H Q03 H H H L H H H Q12 Q11 Q10 B VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 E E0 Q00 Q01 Q02 Q03 A TRUTH TABLE ENABLE INPUTS E L L L L L L H E0 L L L L L H X E1 L L L L H L X INPUTS A L L H H L L X B L H L H L L X Q10 L H H H H L H Q11 H L H H H H H Q12 H H L H H H H Q13 H H H L H H H Q00 L H H H L H H Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). ORDERING INFORMATION Device MC10171L MC10171P MC10171FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail © Semiconductor Components Industries, LLC, 2002 1 January, 2002...