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MC100LVEL38 Datasheet

Part Number MC100LVEL38
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Clock Generation Chip
Datasheet MC100LVEL38 DatasheetMC100LVEL38 Datasheet (PDF)

MC100LVEL38 3.3 V ECL ÷2, ÷4/6 Clock Generation Chip Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the intern.

  MC100LVEL38   MC100LVEL38






Part Number MC100LVEL38
Manufacturers Motorola
Logo Motorola
Description Clock Generation Chip
Datasheet MC100LVEL38 DatasheetMC100LVEL38 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA ÷2, ÷4/6 Clock Generation Chip The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential .

  MC100LVEL38   MC100LVEL38







Clock Generation Chip

MC100LVEL38 3.3 V ECL ÷2, ÷4/6 Clock Generation Chip Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. The Phase_Out o.


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