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MC100LVE222 Datasheet

Part Number MC100LVE222
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Low Voltage 1:15 Differential 12 ECL/PECL Clock Driver
Datasheet MC100LVE222 DatasheetMC100LVE222 Datasheet (PDF)

MC100LVE222 Low Voltage 1:15 Differential ÷1/÷2 ECL/PECL Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single–ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently co.

  MC100LVE222   MC100LVE222






Part Number MC100LVE222
Manufacturers Motorola
Logo Motorola
Description ECL/PECL CLOCK DRIVER
Datasheet MC100LVE222 DatasheetMC100LVE222 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 1:15 Differential ÷ ÷1/ 2 ECL/PECL Clock Driver MC100LVE222 The MC100LVE222 is a low voltage, low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE222 can be used as a simple fanout buffer or outputs can be configured to provide half frequency outputs. The combination of 1x and 1/2x frequencies is flexible .

  MC100LVE222   MC100LVE222







Low Voltage 1:15 Differential 12 ECL/PECL Clock Driver

MC100LVE222 Low Voltage 1:15 Differential ÷1/÷2 ECL/PECL Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single–ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVE222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring a MR pulse to resynchronize any 1/2X outputs. To ensure that the tight skew specification is realized, both sides of any differential output pair need to be terminated identically even if only one side is being used. When fewer than all fifteen pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a side are used, then leave all these outputs open (unterminated). This will maintain minimum output skew. Failure to do this will result in a 10–20ps loss of skew margin (propagation delay) in the output(s) in use. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC supply.


2005-04-26 : D7088    MTW8N60E    MTW8N60E    MBR1550CT    MBR1560    MBR1560CT    MBR1560CT    MBR1560CT    MBR16100CT    MBR1620   


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