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MC100EPT25 Datasheet

Part Number MC100EPT25
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Differential LVECL/ECL to LVTTL Translator
Datasheet MC100EPT25 DatasheetMC100EPT25 Datasheet (PDF)

MC100EPT25 -3.3 V / -5 V Differential ECL to +3.3 V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buf.

  MC100EPT25   MC100EPT25






Part Number MC100EPT26
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 1:2 Fanout Differential LVPECL to LVTTL Translator
Datasheet MC100EPT25 DatasheetMC100EPT26 Datasheet (PDF)

MC100EPT26 3.3 V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. The VBB output allows the EPT26 to be used in a Single-Ended i.

  MC100EPT25   MC100EPT25







Part Number MC100EPT24
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description LVTTL/LVCOMS to Differential LVECL Translator
Datasheet MC100EPT25 DatasheetMC100EPT24 Datasheet (PDF)

MC100EPT24 3.3 V LVTTL/LVCMOS to Differential LVECL Translator Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8-lead package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. Features • 350 ps Typical Propagation Delay • Maximum Input Clock Frequency = > 1.0 GHz Typical • T.

  MC100EPT25   MC100EPT25







Part Number MC100EPT23
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator
Datasheet MC100EPT25 DatasheetMC100EPT23 Datasheet (PDF)

MC100EPT23 3.3 V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator Description The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only + 3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock or data signal. The EPT23 is ava.

  MC100EPT25   MC100EPT25







Part Number MC100EPT22
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
Datasheet MC100EPT25 DatasheetMC100EPT22 Datasheet (PDF)

MC100EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT22 makes it ideal for those applications where space, performance, and low power are at a premium. Because the mature MOSAIC 5 process is used, low cost and high speed can be added to the list of feat.

  MC100EPT25   MC100EPT25







Differential LVECL/ECL to LVTTL Translator

MC100EPT25 -3.3 V / -5 V Differential ECL to +3.3 V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 mF capacitor. Features • 1.1 ns Typical Propagation Delay • Maximum Frequency > 275 MHz Typical • Operating Range: ♦ VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0 V • 24 mA TTL Outputs • Q Output Will Default LOW with Inputs Open or at VEE • VBB Output • Open Input Default State • Safety Clamp on Inputs • These Devices are Pb-Free, Halo.


2005-04-26 : D7088    MTW8N60E    MTW8N60E    MBR1550CT    MBR1560    MBR1560CT    MBR1560CT    MBR1560CT    MBR16100CT    MBR1620   


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