MC100E156

www.DataSheet4U.com MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. Features http://onsemi.com 950 ps Max. D to Output 850 ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC= 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 271 devices Pb−Free Packages are Available* PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxE156FNG AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATI...