MB86978A

FUJITSU SEMICONDUCTOR DATA SHEET w . U 4 Engine t ASSP IPsec e e h S a t a D High-Speed IPsec Processing Engine . w w m o c DS04-22115-4E MB86978A ■ DESCRIPTION MB86978A is IPsec accelerator engine of Inline Architecture. Once setup with appropriate parameters, the device can perform bi-directional 100 Mbps IPsec processing at full wire speed. ■ FEATURES Built-in RMII/MII interface of two ports One interface for WAN (internet) side and one for routing function side Complies with IEEE802.3 (DIX format) Supports 10/100BASE-T/TX, full/half-duplex, and auto-negotiation IEEE 802.3x flow control supported Half-duplex back pressure supported SMI interface for PHY device control ■ PACKAGE 337-pin plastic FBGA w w w .D t a S a e h t e U 4 .c m o (Continued) 288-pin plastic FBGA BGA-337P-M02 BGA-288P-M13 w w w .D at h S a t e e 4U . m o c MB86978A Built-in engine for IKE processing To speed up the calculation processing of IKE, the following functional block is built-in. When IPsec is processed in host CPU, this encryption engine and the authentication engine can be used. DES/3DES : Encryption engine AES : Encryption engine SHA-1 : Authentication engine MD5 : Authentication engine IKE support : Surplus operation engine for RSA and DH processing acceleration Built-in Inline type IPsec processing engine To execute the IPsec processing of a full wire with Inline IPsec, the following functions are installed. (1) Full wire code e...