MAX3882A

19-2718; Rev 2; 4/09 www.DataSheet4U.com 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier General Description The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps parallel data for SDH/SONET applications. The device accepts serial NRZ input data as low as 10mVP-P of 2.488Gbps and generates four parallel LVDS data outputs at 622Mbps. Included is an additional high-speed serial data input for system loopback diagnostic testing. For data acquisition, the MAX3882A does not require an external reference clock. However, if needed, the loopback input can be connected to an external reference clock of 155MHz or 622MHz to maintain a valid clock output in the absence of input data transitions. Additionally, a TTL-compatible loss-of-lock output is provided. The device provides a vertical threshold adjustment to compensate for optical noise generated by EDFAs in WDM transmission systems. The MAX3882A operates from a single +3.3V supply and consumes 610mW. The MAX3882A’s jitter performance exceeds all SDH/ SONET specifications. The device is available in a 6mm ✕ 6mm, 36-pin TQFN package. Features ♦ No Reference Clock Required for Data Acquisition ♦ Serial Input Rate: 2.488Gbps ♦ Fully Integrated Clock and Data Recovery with Limiting Amplifier and 1:4 Demultiplexer ♦ Parallel Output Rate: 622Mbps ♦ Differential Input Range: 10mVP-P to 1.6VP-P without Th...