MACH230-10

FINAL COM’L: -10/15/20 IND: -18/24 MACH230-10/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 128 Macrocells 10 ns tPD Commercial 18 ns tPD Industrial 100 MHz fCNT 70 Inputs 64 Outputs Lattice Semiconductor 128 Flip-flops; 4 clock choices 8 “PAL26V16” blocks with buried macrocells Pin-compatible with MACH130, MACH131, MACH231, and MACH435 GENERAL DESCRIPTION The MACH230 is a member of the high-performance EE CMOS MACH 2 device family. This device has approximately twelve times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH230 consists of eight PAL blocks interconnected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH230 has two kinds of macrocell: output and buried. The output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH230 has dedicated...