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M74HC109 Datasheet

Part Number M74HC109
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Datasheet M74HC109 DatasheetM74HC109 Datasheet (PDF)

M54HC109 M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS109 B1R (Plastic Package) F1R (Ceramic Package.

  M74HC109   M74HC109






Part Number M74HC107
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description DUAL J-K FLIP FLOP
Datasheet M74HC109 DatasheetM74HC107 Datasheet (PDF)

M74HC107 DUAL J-K FLIP FLOP WITH CLEAR s HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: )VNIH = VNIL = 28 % VCC (MIN.) t(ss SYMMETRICAL OUTPUT IMPEDANCE: c|IOH| = IOL = 4mA (MIN) us BALANCED PROPAGATION DELAYS: dtPLH ≅ tPHL ros WIDE OPERATING VOLTAGE RANGE: PVCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH te74 SERIES 107 oleDESCRIPTION bsThe M74HC107 is an high speed CMOS DUAL J-K FLIP FLOP fabricated with sili.

  M74HC109   M74HC109







Part Number M74HC10
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description TRIPLE 3-INPUT NAND GATE
Datasheet M74HC109 DatasheetM74HC10 Datasheet (PDF)

M74HC10 TRIPLE 3-INPUT NAND GATE s s s s s s s HIGH SPEED: tPD = 8ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC10B1R M74HC10M1R T&R M74HC10RM13TR M74HC10TTR DE.

  M74HC109   M74HC109







DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC109 M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS109 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC109F1R M74HC109M1R M74HC109B1R M74HC109C1R DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabri2 cated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going transitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection December 1992 1/11 M54/M74HC109 PIN DESCRIPTION PIN No 1, 15 2, 4, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1CLR, 2CLR 1J, 2J, 1K, 2K 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset Direct In.


2005-05-06 : M68AW031AL70N6U    M68AW031AL70NS6U    M68AW031AM70MS6U    M68AW031AM70N6U    M68AW031AM70NS6U    M68AW064F    M68AW127    M68AW127B    M68AW128M    M68AW511A   


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