January 14, 2003 Rev.0.7
Preliminary
Notice: This is not final specification. Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi'...
