M58LV064B

M58LV064A M58LV064B 64 Mbit (4Mb x16 or 2Mb x32, Uniform Block, Burst) 3V Supply Flash Memories PRELIMINARY DATA FEATURES SUMMARY s WIDE DATA BUS for HIGH BANDWIDTH – M58LV064A: x16 – M58LV064B: x16/x32 s Figure 1. Packages SUPPLY VOLTAGE – VDD = 3.0 to 3.6V M58LV064 core supply – VDDQ = 1.8 to VDD for I/O Buffers s SYNCHRONOUS/ASYNCHRONOUS READ – Synchronous Burst read – Pipelined Synchronous Burst Read – Asynchronous Random Read – Asynchronous Address Latch Controlled Read – Page Read TSOP56 (N) 14 x 20mm TBGA s ACCESS TIME – Synchronous Burst Read up to 66MHz – Asynchronous Page Mode Read 150/25ns – Random Read 150ns TBGA64 (ZA) 10 x 13mm TBGA s PROGRAMMING TIME – 16 Word or 8 Double-Word Write Buffer – 12µs Word effective programming time TBGA80 (ZA) 10 x13mm s s s s s s 64 UNIFORM 64 KWord MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND OTP SECURITY AREA COMMON FLASH INTERFACE 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code M58LV064A: 0015h – Device Code M58LV064B: 0014h s December 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/65 M58LV064A, M58LV064B TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . ...