M54/74HCT125 M54/74HCT126
QUAD BUS BUFFERS (3-STATE)
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HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWE...
M54/74HCT125 M54/74HCT126
QUAD BUS BUFFERS (3-STATE)
. . . . . . .
HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH = 6 mA (MIN.) COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) PIN AND FUNCTION COMPATIBLE WITH 54/74LS125/126
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
DESCRIPTION The M54/74HCT125/126 are high speed
CMOS QUAD BUS BUFFER (3-STATE) FABRICATED IN SILICON GATE C2MOS technology. They have the same high speed performance of LSTTL combined with true
CMOS low power consumption. These devices require the same 3-STATE control input G to be taken high to make the output go into the high impedance state.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with protection circuits against static discharge and transient excess
voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT
ORDER CODES : M54HCTXXXF1R M74HCTXXXM1R M74HCTXXXB1R M74HCTXXXC1R
PIN CONNECTIONS (top view)
HCT125
HCT126
NC = No Internal Connection
October 1993
1/10
M54/M74HCT125/126
CHIP CARRIER
HCT125 HCT126
TRU...