M54HC75
RAD HARD 4 BIT D TYPE LATCH
s
s
s
s
s
s
s
s s
s
s
HIGH SPEED: tPD = 11ns (TYP.) at VCC = 6V LOW POWER ...
M54HC75
RAD HARD 4 BIT D TYPE LATCH
s
s
s
s
s
s
s
s s
s
s
HIGH SPEED: tPD = 11ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING
VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 75 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9203-065
DILC-16
FPC-16
ORDER CODES
PACKAGE DILC FPC FM M54HC75D M54HC75K EM M54HC75D1 M54HC75K1
DESCRIPTION The M54HC75 is an high speed
CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology.
It contains two groups of 2 bit latches controlled by an enable input (G12 or G34). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/10
M54HC75
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Ci...