M48Z35AY

M48Z35AY M48Z35AV 256 Kbit (32Kb x8) ZEROPOWER® SRAM s INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY READ CYCLE TIME EQUALS WRITE CYCLE TIME BATTERY LOW FLAG (BOK) AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): – M48Z35AY: 4.20V ≤ VPFD ≤ 4.50V – M48Z35AV: 2.7V ≤ V PFD ≤ 3.0V 28 SNAPHAT (SH) Battery s s s 28 1 s 1 PCDIP28 (PC) Battery CAPHAT SOH28 (MH) s SELF-CONTAINED BATTERY in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x8 SRAMs 15 A0-A14 VCC s Figure 1. Logic Diagram s s DESCRIPTION The M48Z35AY/35AV ZEROPOWER® RAM is a 32 Kbit x8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. Table 1. Signal Names A0-A14 DQ0-DQ7 E G W VCC VSS April 2000 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground 8 DQ0-DQ7 W E G M48Z35AY M48Z35AV VSS AI02781B 1/16 M48Z35AY, M48Z35AV Figure 2A. DIP Pin Connections Figure 2B. SOIC Pin Connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z35AY 22 8 M48Z35AV ...