M48T128Y
5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low ...
M48T128Y
5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
) ■ BCD coded year, month, day, date, hours, t(s minutes, and seconds c ■ Automatic power-fail chip deselect and WRITE u protection rod ■ WRITE protect
voltage
VCC = 4.5 to 5.5 V; 4.1 V ≤ VPFD ≤ 4.5 V
P (VPFD = power-fail deselect
voltage) te ■ Conventional SRAM operation; unlimited le WRITE cycles so ■ Software-controlled clock calibration for high b accuracy applications O ■ 10 years of data retention and clock operation - in the absence of power t(s) ■ Self-contained battery and crystal in the DIP
package
uc ■ Pin and function compatible with JEDEC d standard 128 K x 8 SRAMs ro ■ RoHS compliant Obsolete P – Lead-free second level interconnect
32 1
PMDIP32 module
September 2011
Doc ID 5746 Rev 7
This is information on a product still in production but not recommended for new designs.
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Contents
Contents
M48T128Y
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
