M3488

M3488 256 x 256 DIGITAL SWITCHING MATRIX . . . . . . . . . . . PREL IMINARY DATA 256 INPUT AND 256 OUTPUT CHANNEL CMOS DIGITAL SWITCHING MATRIX COMPATIBLE WITH M088 BUILDING BLOCK DESIGNED FOR LARGE CAPACITY ELECTRONIC EXCHANGES, SUBSYSTEMS AND PABX NO EXTRA PIN NEEDED FOR NOT-BLOCKING SINGLE STAGE AND HIGHER CAPACITY SYNTHESIS BLOCKS (512 or 1024 channels) EUROPEAN TELEPHONE STANDARD COMPATIBLE (32 serial channels per frame) PCM INPUTS AND OUTPUTS MUTUALLY COMPATIBLE ACTUAL INPUT-OUTPUT CHANNEL CONNECTIONS STORED AND MODIFIED VIA AN ON CHIP 8-BIT PARALLEL MICROPROCESSOR INTERFACE TYPICAL BIT RATE : 2Mbit/s TYPICAL SYNCHRONIZATION RATE : 8KHz (time frame is 125µs) 5V P0WER SUPPLY CMOS & TTL INPUT/OUTPUT LEVELS COMPATIBLE HIGH DENSITY ADVANCED 1.2µm HCMOS3 PROCESS DIP40 PQFP44 ORDERING NUMBERS: M3488B1 M3488Q1 . . . . . . Main instructions controlled by the microprocessor interface CHANNEL CONNECTION/DISCONNECTION OUTPUT CHANNEL DISCONNECTION INSERTION OF A BYTE ON A PCM OUTPUT CHANNEL/DISCONNECTION TRANSFER TO THE MICROPROCESSOR OF A SINGLE PCM OUTPUT CHANNEL SAMPLE TRANSFER TO THE MICROPROCESSOR OF A SINGLE OUTPUT CHANNEL CONTROL WORD TRANSFER TO THE MICROPROCESSOR OF A SELECTED 0 CHANNEL PCM INPUT DATA ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IO Ptot Tstg Top Supply Voltage Input Voltage Off State Output Voltage Current at Digital Outputs Total Package Power Dissipation Storage Temperature Range Operating Temperature Range Parameter Test Conditions -0.3 to 7 -0.3 ...