LY625128

 Rev. 2.9 LY625128 512K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Rev. 2.8 Rev. 2.9 Description Initial Issue Revised ISB1/IDR Revised Test Condition of ICC Added -45ns Spec. Added P-DIP PKG Revised Test Condition of ISB1/IDR Adding PKG type : 44 TSOP-II Adding SL Spec. Revised ABSOLUTE MAXIMUN RATINGS Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Deleted -35ns Spec. Revised VDR Revised PACKAGE OUTLINE DIMENSION in page 11/12/13/14 Revised ORDERING INFORMATION in page 16 Deleted PKG type : 44 TSOP-II Revised VIL(max) from 0.6V to 0.8V Revised ORDERING INFORMATION in page 18/19 Revised TEST CONDITION of ICC/ICC1/ISB1 in DC ELECTRICAL CHARACTERISTICS(page 5) and IDR in DATA RETENTION CHARACTERISTICS(page 9) Deleted WRITE CYCLE Notes : 1. WE#,CE# must be high during all address transitions. in page 8 Revised ORDERING INFORMATION in page 16 Issue Date Jul.19.2005 Oct.31.2005 Sep.20.2006 Jan.12.2007 May.14.2007 Jun.4.2007 Jul.11.2007 Mar.30.2009 Sep.11.2009 May.7.2010 Aug.30.2010 Feb.21.2012 May 8.2014 May 22.2015 Jun.2.2015 Jun.29.2016 Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No.17, Industry E...