LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
DESCRIPTION
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their...
