Ordering number : EN*5391
NMOS + CCD
LC89975M
PAL-Format Delay Line
Preliminary Overview
The LC89975M is a lower-cost PAL-Format CCD delay line based on the LC89970M, with the sizes of chip and package miniaturized and the external parts count reduced. • • • • • • • Auto-bias circuit Sync tip clamping circuit (luminance signal) Center bias circuit (chrominance signal) Sample-and-hold circuit PLL 3× circuit 3·fsc clock output circuit RD voltage generation step-up circuit
Features
• 5 V single-.
PAL-Format Delay Line
Ordering number : EN*5391
NMOS + CCD
LC89975M
PAL-Format Delay Line
Preliminary Overview
The LC89975M is a lower-cost PAL-Format CCD delay line based on the LC89970M, with the sizes of chip and package miniaturized and the external parts count reduced. • • • • • • • Auto-bias circuit Sync tip clamping circuit (luminance signal) Center bias circuit (chrominance signal) Sample-and-hold circuit PLL 3× circuit 3·fsc clock output circuit RD voltage generation step-up circuit
Features
• 5 V single-voltage power supply • On-chip 3× PLL circuit for 3·fsc operation from an fsc (4.43 MHz) input • Supports PAL/GBI and 4.43 NTSC systems, selected by a control pin input • Includes an on-chip comb filter for chrominance signal crosstalk exclusion. This adjustment-free circuit provides high-precision comb characteristics. • Peripheral circuits included on chip to allow operation with minimal external circuits. • Positive-phase signal input, positive phase signal output (luminance signal)
Package Dimensions
unit: mm 3111-MFP14S
[LC89975M]
Functions
• CCD shift register (for chrominance and luminance signals) • CCD drive circuit • Circuit for switching the number of CCD stages • CCD signal addition circuit
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD Pdmax Topr Tstg Conditions Ratings –0.3 to +6.0 250 –10 to +60 –55 to +150 Unit V mW °C °C
Recommended Conditi.