KM416S4030C

KM416S4030C Revision History Revision 1 (May 1998) - ICC2 N value (10mA) is changed to 12mA. Preliminary CMOS SDRAM Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 KM416S4030C 1M x 16Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Preliminary CMOS SDRAM GENERAL DESCRIPTION The KM416S4030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. KM416S4030CT-G/F7 KM416S4030CT-G/F8 KM416S4030CT-G/FH KM416S4030CT-G/FL KM416S4030CT-G/F10 Max Freq. 143MHz 125MHz 100MHz 100MHz 100MHz LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register...