K7I323682M

K7I323682M K7I321882M Document Title 1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM 1Mx36 & 2Mx18 DDRII CIO b2 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Pin name change from DLL to Doff. 2. Vddq range change from 1.5V to 1.5V~1.8V. 3. Update JTAG test conditions. 4. Reserved pin for high density name change from NC to Vss/SA 5. Delete AC test condition about Clock Input timing Reference Level 6. Delete clock description on page 2 and add HSTL I/O comment 1. Update current characteristics in DC electrical characteristics 2. Change AC timing characteristics 3. Update JTAG instruction coding and diagrams 1. Add AC electrical characteristics. 2. Change AC timing characteristics. 3. Change DC electrical characteristics(ISB1) 1. Change the data Setup/Hold time. 2. Change the Access Time.(tCHQV, tCHQX, etc.) 3. Change the Clock Cycle Time.(MAX value of tKHKH) 4. Change the JTAG instruction coding. 1. Change the Boundary scan exit order. 2. Change the AC timing characteristics(-25, -20) 3. Correct the Overshoot and Undershoot timing diagrams. 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Change the operating current parameter. before after Icc(x36) -25 : 620 700 -20 : 520 600 -16 : 440 500 Icc(x18) -25 : 560 670 -20 : 470 570 -16 : 410 470 Icc(x 8 ) -25 : 540 650 -20 : 450 550 -16 : 390 450 Isb1 -25 : 200 230 -20 : 18...