K4S643232F

K4S643232F CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.0 January 2002 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 (Jan. 2002) K4S643232F Revision History Revision 1.0 (January 16, 2002) Defined DC spec. CMOS SDRAM Revision 0.1 (September 03, 2001) - Preliminary Added K4S643232F-TC/L55 Revision 0.0 (September 03, 2001) - Target Spec Initial draft -2- Rev. 1.0 (Jan. 2002) K4S643232F 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency ( 2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle CMOS SDRAM GENERAL DESCRIPTION The K4S643232F is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OR...