K4S641632D
CMOS SDRAM
64Mbit SDRAM
1M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.3 June 2000
* Samsung Elec...
K4S641632D
CMOS SDRAM
64Mbit SDRAM
1M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.3 June 2000
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 June 2000
K4S641632D
Revision History
Revision 0.1 (May 2000)
Changed tOH of K4S280432C-TC75/TL75 from 2.7ns to 3.0ns.
CMOS SDRAM
Revision 0.2 (May 2000)
Added -70 (7.0ns) Speed.
Revision 0.3 (June 2000)
Added -60 (6.0ns) and -55(5.5ns) Speed.
Rev. 0.3 June 2000
K4S641632D
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance
CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
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