K4S640832F-TL75

K4S640832F CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 May. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev.1.1 May. 2003 K4S640832F Revision History Revision 0.0 (June, 2001) Revision 0.1 (Sep., 2001) CMOS SDRAM Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Revision 1.0 (May, 2003) Revision Changed (Confirmed revision will be 1.0) Revision 1.1 (May, 2003) Delete 100MHz speed Rev.1.1 May. 2003 K4S640832F 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S640832F is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows pr...