K4S56163LC

K4S56163LC-R(B)F/R CMOS SDRAM 16Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR) Revision 1.4 December 2002 Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R 4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES 2.5V power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation. Special Function Support. -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). DQM for masking. Auto refresh. 64ms refresh period (8K cycle). Commercial Temperature Operation (-25° C ~ 70 °C). 54balls CSP (-RXXX - Pb, -BXXX - Pb Free). K4S56163LC-R(B)F/R75 K4S56163LC-R(B)F/R1H K4S56163LC-R(B)F/R1L K4S56163LC-R(B)F/R15 CMOS SDRAM GENERAL DESCRIPTION The K4S56163LC is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance ...